Design and Evaluation of Chase Decoder Architecture for Medium Capacity TDMA Satellite Systems DOI: 10.14209/jcis.1990.6 - César A. S. Salles, Hélio; da Cunha Borelli, Walter (Journal of Communication and Information Systems, 2015)
This paper describes a digital machine architecture suitable for soft-decision decoding of binary linear block error-correcting codes, based on Chase’s algorithm II. Specifically, it is presented the hardware implementation for the extended Golay (24, 12, 8) block code in a printed circuit board used in a satellite multi-lrequency TDMA data transmission system, called SAMSAT, which was developed at CPqD-TELEBRÁS. This architecture may be implemented using off-the-shelf digital ICs and still reach up to 1 Mbil/s transmission rates, in a variety of digital satellite transmission applications. Cost and chip count of final circuitry are highly competitive within the class of performance to which this forward-error-correction (FEC) technique pertains.