Fast Hardware Design of 1/f Fractional Brownian Noise Generator

  • G. Loss
  • R. Coelho

Abstract

This paper proposes the design of a fast and accurate 1/f fractional Brownian motion (fBm) noise generator. The solution is based on the successive random addition algorithm using the midpoint displacement (SRMD) technique. The implementation was performed on a high-speed field-programmable gate array (FPGA) Development Kit. It enabled the generation of 150 million of 16-bit noise samples per second. The 1/f noise generator achieved 7.4% of the logic elements, 52% of the RAM memory and 1.6% of the ROM memory. The accuracy of the 1/f noise samples was evaluated for different sequence size and confidence intervals. The noise samples pattern was examined by the probability density (PDF) and the heavy-tail distribution (HTD) functions. The results also include the auto-correlation function (ACF) to show the low-frequency statistics of the 1/f noise samples. For the investigation it was used the real 1/f speech-babble acoustic noise parameters. The results showed that the proposed 1/f noise generator design can be promising to the performance evaluation of communications channels with low bit error rate (BER) values. It can also be interesting for signal processing applications and other areas concerned with noisy conditions.
Published
14-06-2015
How to Cite
Loss, G., & Coelho, R. (2015). Fast Hardware Design of 1/f Fractional Brownian Noise Generator. Journal of Communication and Information Systems, 26(1). https://doi.org/10.14209/jcis.2011.2
Section
Regular Papers