An Analog Filter Bank-based Circuit for Performing the Adaptive Impedance Matching in PLC Systems

—Aiming to bring attention to the necessity of dealing with the dynamics of access impedance in electric power systems, this paper introduces an adaptive impedance matching circuit that is based on an analog ﬁlter bank approach. In this sense, it describes a prototype that validates the proposed ﬁlter bank approach for improving impedance matching. Numerical results obtained with the detailed prototype operating in the frequency band between 2 and 500 MHz show that the proposed analog ﬁlter bank approach helps to improve impedance matching in power line communication (PLC) systems. Also, the numerical results show that the dynamics of impedance matching between two or more PLC transceivers is a difﬁcult task to be accomplished because real-time coordination among them is necessary. Overall, it is shown that the proposed analog ﬁlter bank approach constitutes an interesting research direction for improving impedance matching between PLC transceivers and electric power systems.

impedance of electric power systems changes in the time and frequency domains due to the dynamics of loads [6]. Regarding only the frequency domain, literature has shown that access impedance exhibits frequency selectivity for the frequency bandwidths occupied by narrowband and broadband PLC systems, constituting a rather tricky scenario to achieve impedance matching [6]- [8] effectively. However, the effective design of impedance matching circuit between PLC transceivers and electric power systems plays a vital role in maintaining the appropriate signal strength at the point of connection with electric power systems. In other words, it has to be accomplished to assuring the maximum power transfer that positively impacts reliability or data rate of PLC systems [9]. The dynamics of the access impedance of electric power systems at the point of connections have consistently been recognized as one of the significant weaknesses of PLC systems [10].
Few contributions address impedance mismatching between PLC transceivers and electric power systems [11]- [13] since loads mainly control the dynamics of impedance access in electric power systems, and these loads can hardly be controlled. Therefore, typical PLC coupling circuits present an optimum performance only at the frequency at which the impedance of electric power systems and the PLC coupling circuits match. Variations on the topology of electric power systems combined with an unknown power cable and load access impedance changes constantly the impedance matching of PLC coupling circuits based on the use of constant input/output impedance. Recent research findings suggest a manual adaptation of the access impedance of PLC transceiver to ensure its value is roughly equal, on average, to a chosen electric power systems impedance by changing the turns winding ratio 1 : N of a Radio Frequency (RF) transform [14], [15]. In [16], the authors proposed two different PLC coupling circuits, incorporating a 4 : 1 and 2 : 1 winding ratio for permanent connection between PLC transceivers and electric power systems for impedance matching purpose. As reported in [17], typical residential rooms are classified to propose proper coupler winding ratios for impedance adaptation. Couplers with specific access impedance values can result in substantial transmission gains. Regardless of the topology of electric power systems, gains up to 10 dB can be attained [17].
Regarding the adaptive PLC coupling circuits for impedance matching, it is well-established that the previous investigations have not introduced solutions for all scenarios. For instance, [9], [18] considering flaws of size, cost, and performance while [19] discussing in a coupling circuit, which is dynamically adapted by tuning its inductors and the RF transform of the PLC coupling circuit with a fuzzy logic technique implemented in a microcontroller. Also, [20] discussed a voltage controllable inductance circuit, which is composed of an operational amplifier, for performing impedance matching through the use of a voltage controllable inductance circuit. In [21], the authors emphasized the benefits of active inductors over a tapped transformer and the use of a digital variable capacitor controlled by a microcontroller. Transformerless impedance matching circuits combined with capacitor banks and active inductor topologies were proposed in [22]. In [23] was introduced an adaptive impedance matching circuit that automatically tries to match impedance, changing the tap of the RF transformer, which is controlled by a microcontroller that makes use of a feedback circuit for measuring the reflected power of the signal injected by PLC transceivers into electric power systems.
A critical aspect of impedance matching is the frequency bandwidth. The Smith Chart gives a good match at a single frequency, but a broadband design is often required. The Bode-Fano criterion [24] relates the quality of the matching to the frequency bandwidth. This criterion shows that a perfect match is only possible if we assume very narrow frequency bandwidth or a single frequency. Broadband impedance matching with cascaded L-Networks is accomplished by cascading more sections of filters with additional intermediate impedance, creating lower impedance rates and correspondingly lower Qfactor for each filtering section. However, it depends on the loads and electric power systems impedance, which vary in time and frequency. Consequently, a PLC coupling circuit needs an adaptation in the cascade L-Networks every time access impedance of electric power systems impedance change to ensure maximum power transfer [12]. The effectiveness of the impedance matching based on L-Networks depends on the insertion loss level.
Aiming to improve the impedance matching between PLC transceivers and electric power systems, this paper introduces the use of an analog filter bank approach to come up with feasible adaptive PLC coupling circuits. In this sense, the filter bank-based impedance matching circuit measures the received signal's power and compares it with a typical value memorized in a control unit. It switches between different impedance matching circuits (analog and low-pass filters), which are supposed not to reflect signals in their band-pass to the source, for performing impedance matching in the chosen frequency band. The main contributions of this study are summarized as follow: • The formulation of impedance mismatching for PLC systems as a problem that is time-varying and frequency selective, and, as a consequence, the discussion about the necessity of adapting the access impedance of PLC transceivers to deal with the dynamics of electric power systems is well-posed. • The discussion on the principle of divide and conquer, the coherence bandwidth, and the coherence time to introduce a filter bank approach for performing adaptive impedance matching. Based on this approach and assuming that the number of analog filters in the filter bank is correctly designed, the impedance matching can theoretically be accomplished.
• A detailed description of the prototype of an adaptive, broadband, capacitive, Single Input Single Output (SISO), and low-voltage (LV) PLC coupling circuit for validating the proposed approach. The prototype implements a filter bank-based impedance matching circuit that is controlled by a microcontroller. This prototype covers the frequency bands of 2 − 50 MHz, 2 − 100 MHz, and 2 − 500 MHz. Also, discussions about the performance of the prototype in three setup arrangements are outlined.
Based on the numerical results, the following statements deserve attention: • The analog filter bank approach is an appealing research direction when frequency bandwidth is broad, and the access impedance of electric power systems is timevarying and frequency selective. Also, it was shown that the coherence bandwidth of the magnitude of the access impedance is the correct parameter to guide impedance matching because the impedance is almost constant in a frequency bandwidth shorter than the coherence bandwidth. Moreover, if it is performed in a time interval shorter than the coherence time of the access impedance of electric power systems, then the time-varying behavior can be handle in an elegant manner. Under this constraint, the adaptive coupling circuits can be designed for accomplishing impedance matching purposes. • The implemented prototype shows that the access impedance of PLC transceivers adapts by switching among the circuits belonging to the analog filter bank, which results in feasible adaptive PLC coupling circuits if the complexity of the analog filter bank (i.e., the number of analog filter) is small. Numerical results show that the best impedance matching is achieved for the PLC coupling circuits with an input impedance of 50 Ω and 100 Ω while the PLC coupling circuits with an input impedance of 25 Ω offered the worst results in terms of S 11 (f ) and S 12 (f ) scattering parameters.
• The setup arrangements for characterizing S 11 (f ) and S 21 (f ) scattering parameters show important information concerning attenuation and reactive behaviors of electric power systems, mainly in the presence of the adaptive PLC coupling circuit operating in the frequency band of 2−500 MHz. Also, numerical results of S 11 (f ) scattering parameter show that it may be challenging to perform impedance matching between two or more adaptive coupling PLC circuits because real-time coordination among them may be necessary.
The remainder of this paper is organized as follows: Section II formulates the impedance mismatching problem related to PLC systems; Section III discusses the analog filter bank approach for performing impedance matching by PLC transceivers; Section IV outlines the implementation of the adaptive, broadband, capacitive, SISO and LV PLC coupling circuit based on the analog filter bank approach; experimental results are presented in Section V while concluding remarks are stated in Section VI.

II. PROBLEM FORMULATION
Several practical questions arise concerning the impedance mismatching in narrowband and broadband PLC coupling circuits. For instance, electric power systems differ considerably in terms of topologies, connected loads, physical characteristics of the electromagnetically unshielded power cables, types of soils, and the distances from the soil and between power lines.
Considering electric power systems be time-varying systems, we can use the two-wire transmission line theory to adapt two-port ABCD matrices to model the signal propagation and analyze impedance mismatching [25], [26] in a time-varying scenario. Fig. 1 shows a model based on the ABCD matrix that can be used to analyze the impedance mismatching problem related to PLC systems. This model emphasizes that PLC transceivers and electric power systems are time-varying systems. Noting that electric power systems time-varying behavior is mainly associated with load dynamics owned by electric utilities and consumers. Also, since the coherence time of in-home and LV is lower than 600 µs [27], [28] and around 1000 µs for outdoor and LV electric power systems, we can assume during these time intervals that electric power systems are time-invariant systems, and consequently they can be modeled by a well-known ABCD matrix. In other words, during the time interval t ∈ [0, T c ], in which T c denotes the coherence time of the PLC channel, the ABCD matrix presents irrelevant changes, and T c can be seen as a great approximation of the coherence time for the access impedance of electric power systems.
According to Fig. 1, we have in which V T X (f, t) is the voltage source with Z T X (f, t) internal impedance; V 1 (f, t) and I 1 (f, t) are, respectively, the voltage and current at the input port of the electric power circuit; V 2 (f, t) and I 2 (f, t) are the voltage and current at the output port of the electric power circuit, respectively; is the voltage at the input port of the PLC transceiver; Z RX (f, t) is the impedance at the input port of the PLC transceiver; and Z 1 (f, t) and Z 2 (f, t) are the access impedance at the input and output port of the electric power circuit, respectively. Note that which is the voltage at the input port of the two-port ABCD of the electric power circuit. The voltage V RX (f, t) at the receiver of the PLC transceiver, which has an impedance Z RX (f, t), is given by The relations between the input and output ports of the twowire transmission line showed in Fig. 1 can be obtained using Note that the two-port network can be written as a function of the input impedance parameters, Z 1 (f, t), of an electric power circuit. It can be obtained by time-varying ABCD matrix, see (1). As a result, It means that the input access impedance parameter of the electric power circuit depends on the time-varying behavior of input impedance Z RX (f, t) of the PLC transceiver and ABCD matrix of the electric power circuit [29]. Thus, we can conclude that to maximize the power transfer from the transmitter to the receiver, the PLC coupling circuit must be designed to precisely match the time-varying behavior of the impedance of input and output ports of an electric power circuit. Also, such circuit is modeled as a time-varying ABCD matrix, with the Z T X (f, t) and Z RX (f, t) impedance of the PLC transmitter and receiver, respectively. The use of concepts of impedance matching and ABCD matrix can help to understand the impedance mismatching between PLC transceivers and electric power systems when the dynamics of loads are taken into account. For instance, in Fig. 1, Z 1 (f, t) represents the impedance of the electric power system seen by the transmitter of the PLC transceiver, which could be matched with the impedance Z T X (f, t). On the other hand, Z 2 (f, t) is the electric power systems impedance seen by the Z RX (f, t) impedance of the PLC transceiver. Note that Z T X (f, t) = Z 1 (f, t) and Z RX (f, t) = Z 2 (f, t) means that maximum power transfer occurs between PLC transmitter and electric power systems and between electric power systems and PLC receiver, respectively.
At this moment, it is important to emphasize that the access impedance of electric power systems is continuously changing as time evolves. Consequently, it is challenging to achieve perfect impedance matching if Z RX (f, t) and Z T X (f, t) are not designed by taking into account the time variable, t, (i.e., the time-varying behavior of electric power systems).
Based on this scenario, it is clear that the impedance matching between PLC transceivers and electric power systems demand the design of the adaptive PLC coupling circuits that are capable of detecting variations of access impedance of electric power systems and dynamically adjust the impedance of the coupling circuit. Section III outlines an approach to deal with this problem.

III. ANALOG FILTER BANK APPROACH FOR IMPEDANCE
MATCHING Let Z(f, t) be the access impedance of an electric power system, such as −∞ < t < +∞, B ∈ R + | |f | B is the frequency bandwidth in Hertz. Then, the following definitions apply: Definition 1. The coherence time of Z(f, t) is denoted by T z ∈ R + . The coherence time of the access impedance refers to a time interval duration in which Z(f, t) ≈ Z(f, t + ∆t) subjected to ∆t ∈ R + | ∆t T z . The coherence time is defined by T ransmitter part of a P LC transceiver T wo − wire transmission line ABCD model Receiver part of a P LC transceiver in which α ∈ R + | 0 < α < 1, | | is the absolute value operator and * is the complex conjugate operator.
Based on the aforementioned definitions, the following theorems apply: Theorem 1. Let the access impedance of an electric power system be given by Z(f, t) ∈ C, then Z(f + ∆f, t + ∆t) = Z for ∆f ∈ R + |0 ∆f B z and ∆t ∈ R + |0 ∆t T z .
Proof. According to [28], [30], the data communication channel between two PLC transceivers become time-invariant during a period shorter than the so-called coherence time of PLC channel, T c . In addition, [31]- [33] states that the frequency response of any quantity can be constant in a frequency bandwidth shorter than the so-called coherence bandwidth. Assuming that T z ≈ T c , which is an acceptable assumption due to the intrinsic relationship among the scattering parameters and the value of the coherence bandwidth of the access impedance of electric power systems, it is easy to conclude that Z(f + ∆f, t + ∆t) = Z for 0 ∆f B z and 0 ∆t T z . Lemma 1. In the n th time interval denoted by T zn ∈ [nT z t (n + 1)T z ], the value of the access impedance in the k th frequency sub-band, which occupies (2k − 1)B z /2 f (2k + 1)B z /2, is a constant value denoted by Z k,n ∈ C.
Proof. Let us assume that T c is long enough for processing Z(f, t) during the n th time interval, then the impedance matching between PLC transceivers and electric power systems, in the whole frequency band, can be accomplished by using the principle of divide and conquer. The use of this principle in the impedance mismatching problem results in the decomposition of the broadband impedance mismatching problem into J ∈ N|J ⌈B/B z ⌉, where ⌈x⌉ = min l ∈ N | l > x, narrowband and parallel impedance mismatching problems. Constant impedance values characterize these problems because the Theorem 1 states that during the n th time interval, the access impedance of electric power systems can be approximated by a piece-wise constant function within the frequency band shorter than B z . Consequently, impedance matching can be easily designed for each constant piece of the frequency response of the access impedance, which is supposed to be time-invariant in a time interval shorter than T z .
The implementation of the Lemma 1 for performing impedance matching between PLC transceivers and electric power systems can be accomplished by using a bank of J impedance matching sub-circuits with each of them designed to match a constant impedance in a bandwidth equal to B z . In this sense, the block diagram of the so-called impedance matching circuits bank for a PLC transceiver is shown in Fig. 2. According to this block diagram, the bank of impedance matching circuits can be divided into four main parts: the interface with electric power systems, two switching banks, the impedance matching circuits bank, and the control unit. Note that J sub-circuits constitute the m th impedance matching circuit for performing impedance matching in the J sub-bands of frequency bandwidth equal to B z , which is a consequence of using the principle of divide to conquer. Based on the summation of the signal available at the outputs of the Switch Bank #2, the Control Unit applies a control algorithm to simultaneously control the Switch Banks #1 and #2 to select the best impedance matching and to ensure that the impedance matching is accomplished in a time interval shorter than T z . It is important to emphasize that as long as T z → ∞, the switching process facilitates because electric power systems tend to be time-invariant ones.
where 1 ≤ m ≤ M , N ∈ N is the number of samples, v[m, i] is the i th sampled value from the j th output of the Switch Bank #2. The j th impedance matching circuit offering the highest average power is chosen to perform impedance matching. Note that other values, such as the average signal value, can be applied to reduce computational complexity. Using the Control Unit and the Switch Banks #1 and #2, the impedance matching can be accomplished through two different strategies, which are described as follows: • Strategy #1: Each impedance matching sub-circuit is designed to match the access impedance associated with one frequency sub-band, which occupies a frequency bandwidth equal to B z . This strategy may result in the best impedance matching results. Indeed, if B z → 0 (i.e., J → +∞), then the impedance matching circuits bank tends to correctly perform the impedance matching between PLC transceivers and electric power systems with a large number of matching circuit in parallel and, as a consequence, it may show it may result in an unfeasible and costly solution because of the considerable hardware complexity. Therefore, a careful choice of J and M may result in a reasonable trade-off between performance and complexity. • Strategy #2: All impedance matching sub-circuits are designed to match the access impedance associated with the whole frequency band (i.e., B z = B), which imposes J = 1. If the frequency bandwidth of the access impedance, B, is small, and consequently, the corresponding magnitude of the frequency response is flat, then the impedance matching can be easily accomplished with well-known techniques. This strategy can offer an impedance matching performance that depends upon the frequency selectivity of the access impedance in the whole frequency band. Moreover, it results in a feasible and not expensive solution because the hardware complexity is reasonable if a careful choice of M applies. It is important to emphasize that the impedance matching circuits bank can be feasible and reasonably effective if the following issues are correctly addressed: • The number of impedance matching circuits JM must be carefully chosen because it dictates the hardware complexity. For practical reasons, J and M must be small (e.g., J ≤ 5 and M ≤ 5). • The correct specification of switches because their transients can remarkably influence the overall performance. • The choice of reflectionless analog filters are advantageous because they do not reflect signals in their stopbands back to the source. Also, the analog filters must be capable of matching with a pre-specified set of impedance values covering the frequency bandwidth equal to B z . • The choice of impedance matching circuits has to match the access impedance of electric power systems in some sense; otherwise, it will not be effective.

IV. VALIDATION THROUGH A PROTOTYPE: THE IMPLEMENTATION OF STRATEGY #2
The main objective of a PLC coupling circuit is to perform impedance matching and filter the undesirable signals with simple, effective, and low-cost electronics. In this regard, this section addresses the implementation of Strategy #2, in which the analog filter banks are responsible for implementing the impedance matching circuits. Each impedance matching circuit is designed to offer a reasonable trade-off between performance and complexity, leading to good power transfer between PLC transceivers and electric power systems.
Based on the Strategy #2, Fig. 3 shows the schematic of an adaptive, broadband, capacitive and SISO PLC coupling circuit for LV electric power systems operating in frequency bands of 1.7 − 50 MHz, 1.7 − 100 MHz, and 1.7 − 500 MHz, in which J = 1 and M = 3. We can see that it is constituted by interface and protection circuits to connect it to an electric power system, an analog filter bank, and switching for performing impedance matching, a microcontroller, and a logarithmic amplifier for implementing the Control Unit. Note that J = 1 and M = 3 result in a low complex hardware implementation.
The top and bottom (layers view) of the two-layer fiberglass printed circuit board (PCB) of this adaptive PLC coupling circuit, that was designed in Altium software, are shown in Figs. 4 and 5, respectively. The PCB was designed following the microstrip technique [34], and only Surface Mounted Device (SMD) components were used because their usage reduces the PCB area and covers the chosen frequency bands. Tab. I lists the components used for implementing this adaptive PLC coupling circuits. Details about the main parts of the adaptive, broadband, capacitive, SISO and LV PLC coupling circuit are given in the following subsections.     Fig. 4 and Fig. 5, show that the connection with an electric power system is through a KRE connector labeled J 1 . The connector J 1 is followed by a protection circuit composed of a varistor V R 1 and a capacitor C 1 . The varistor aims to protect the circuit against voltage transients while the capacitor blocks the mains voltage. The RF transformer named TC1-1TX+ (T 1 ), which operates in the frequency band of 0.4 − 500 MHz [35], is chosen to achieve galvanic isolation and to offer the desired voltage ratio.

B. Switch Banks
The primary purpose of the RF Switch Banks is to route signals through the analog filters with the lowest insertion loss, the highest return loss, and the highest isolation between the interface with the electric power system and the output of the impedance matching circuits bank (i.e., the analog filter bank). The control unit controls the switches operational state. Only two switches are selected in an operational state, and only one analog filter of the impedance matching circuits bank is used, while the other M − 1 switches present a high impedance in their ports.
In Fig. 3, the components SW 1−1 , SW 1−2 , SW 1−3 , SW 2−1 , SW 2−2 and SW 2−3 refer to the switch devices. In this prototype, the switch PE 4239 [36] is chosen because it covers the frequency band from DC up to 3.0 GHz. This switch is a single-pole and double-throw (SPDT) -1 : 2, which routes signals from one input to two output paths with an insertion loss of 0.7 dB at 1 GHz. This switch integrates on-board CMOS control logic with a low-voltage CMOScompatible control interface controlled with either single-pin or complementary control inputs. Fig. 6 shows the block diagram of the switch PE 4239 in which the pins RF 1 and RF 2 are the output pins while the pin RF C is the input of the signal. The signal is switched to the pin RF 1 or RF 2 based on the voltage level applied to the CT RL pin. C. Impedance matching circuits bank This subsection details the impedance matching circuits bank (i.e., analog filter bank), which is used in the prototype. In this regard, it is necessary to know the values of access impedance values of electric power systems. According to [31], 90% of the input resistance values measured are between 25 Ω and 100 Ω and the mean value equal to 50 Ω. Therefore, three analog filters (M = 3) are designed with the input resistance equal to 25 Ω, 50 Ω, and 100 Ω. The analog filters are low-pass because the signal is transmitted in the baseband. These three analog filters are designed considering input and output impedance ratios of 1 : 2 (25 to 50 Ω), 1 : 1 (50 to 50 Ω), and 2 : 1 (100 to 50 Ω), where 50 Ω is the input impedance of the PLC transceiver. Also, first (25 to 50 Ω) and third (100 to 50 Ω) analog filters are low-pass irregular ones while the second analog filter (50 to 50 Ω) is a low-pass Chebyshev one. Note that the analog filters output impedance must be matched to 50 Ω for ensuring 1 : 2, 1 : 1, and 2 : 1 ratios. Also, the input and output impedance ratios must be effective in the frequency bandwidths of the PLC coupling circuit, which are 2−50 MHz, 2−100 MHz, and 2−500 MHz.
Tab. II lists the the specifications applied to design the lowpass irregular analog filters and low-pass Chebyshev analog filter with Z in equal to 25 Ω, 50 Ω and 100 Ω, and cutoff frequency, f c , of 50 MHz, 100 MHz, and 500 MHz. It is important to emphasize that the design of analog filters to perform broadband impedance matching is a very complicated task to be accomplished, and excellent results can be attained by using more complex circuits. However, we will focus on cost-effective analog filters that show the analog filter bank approach as a great potential for impedance matching purposes. See numerical results in Section V. Details about these analog filters, which are designed to perform impedance matching with the termination of unequal impedance at the input and output ports, and their design are presented in the following subsections. 1) Low-pass irregular analog filter: This subsection details the use of an approximation function for broadband impedance matching, which results in low-pass irregular analog filters of even order. These types of analog filters are useful to perform impedance matching when the frequency band is broad. Fig. 7 illustrates the frequency response of a lowpass irregular analog filter |H(f )|. Note that |H(f x )| = 1 √ 2 corresponds to the 3 dB cut-off frequency, 1 √ 1 + ε 2 is the ripple of magnitude response, f ′ x and f x are the band-pass limits. This graph assumes a normalization process in which f x = 1 Hz. Note that the normalization process is applied to perform the filter design. The magnitude of the low-pass irregular analog filter is given by [37] |H (f )| = 1 where the characteristic function K(f ) is obtained from the Feldtkeller's equation. The band-pass, which is defined between f ′ x and f x , and the stop-band, which cover f > f x , specifications must be satisfied by characteristic function K(f ). Notice that K(f ) is defined to ensure that |K(f )| 2 approximates to zero in the stop-band with a band-pass attenuation error or band-pass ripple given by ε ∈ R with K(f ) = F (f )/P (f ) being an even rational polynomial function ratio, F (f ) the reflection zero polynomial, and P (f ) is the transmission zero polynomial [37]. The characteristic function between f ′ x and f x is given by where ε ∈ R * + is a constant which is calculated in function of the source impedance Z S (f ) = Z S ∈ R * + and the output impedance Z L (f ) = Z L ∈ R * + impedance terminations, as shown in Fig. 8.
As stated in Section II, the impedance matching between PLC transceivers and electric power systems must cover the entire frequency band. Also, the low-pass irregular analog filters, showed Fig. 8, must be designed with low order and low-quality factor "Q" to cover the entire band of frequency. Aiming to develop low-cost implementation, we decide in favor of a 4 th order low-pass irregular analog filters. It is essential to mention that the low-pass irregular analog filter designed with the structure composed of the components L 1 , L 2 , C 2 , and C 3 must be selected if the output impedance Z L is bigger than electric power system impedance Z S . Nonetheless, if the electric power system impedance Z S is bigger than the output impedance Z L , the designed low-pass irregular analog filter is constituted by the components C 6 , C 7 , L 6 , and L 7 must be selected. P in is the power delivered by the input port of the low-pass irregular analog filter, and P out is the power delivered to output impedance Z L . Fig. 8: The electric circuits of the designed low-pass irregular analog filters for the adaptive PLC coupling circuit.
The transduction or attenuation function T (f ) = E(f )/P (f ) corresponding to this characteristic function is obtained by solving the Feldtkeller's equation, which is given by In this way, the ratio between K(f ) and the so-called transduction function T (f ) is expressed as because Z I (f ) = Z I ∈ R * + is the input impedance of the low-pass irregular analog filter in Fig. 8 and ρ 1 (f ) is the reflection function [26]. Equating (11), From F (f ) and E(f ), the input impedance or admittances of the low-pass irregular analog filters between the terminations can be found, and the obtained circuit, showed in Fig. 8, can be obtained. For the low-pass irregular analog filter, the relation between the output impedance Z L and the electric power system impedance Z S , is expressed as [25] where T (0) and K(0) denote the values in which the transduction function for ρ 1 (0) offers the maximum power transfer (i.e., at f = 0). As both impedance Z L and Z S are connected at the output and input of the low-pass irregular analog filter, a double matched LC network with maximum power transfer is desired in the middle of the band-pass (e.g., f ′ x ). Notice that the input impedance of the low-pass irregular analog filter Z I must be real and match with the electric power system impedance Z S . Also, impedance matching with Z I = Z S and, consequently, equals Z L , provides the maximum power transfer. According to [37], we obtain A key limitation of this design is the relation between output impedance Z L and electric power system impedance Z S . Based on (13) it is straightforward to write or For the sake of simplicity, we have and The ratio between electric power system impedance Z S and output impedance Z L , in (18), defines the value of output and input impedance, respectively. When the constant γ = √ 2 applies, which represents −3 dB cut-off frequency, a ratio of 1 : 5.828 is obtained. However, this ratio between the output impedance Z L , which is fixed in 50 Ω, and the electric power system impedance Z S is not adequate because the value 1 : 5.828 results in an input impedance of Z S = 8.579 Ω, which  is not a desired impedance value and outside the range of the desired access impedance value of electric power systems (i.e., between 25 Ω and 100 Ω, see [31]). In this sense, the low-pass irregular analog filter has been redesigned to obtain a ratio between electric power system impedance Z S and output impedance Z L equal to 1 : 2 and 2 : 1, as a consequence, to lock the input impedance of the low-pass irregular analog filter at 25 Ω and 100 Ω. According to (13), a new value of ε = 0.353553390593 is obtained, and the cut-off point of the low-pass irregular analog filter is applied to the new value f x = 1.6376 Hz. The ratio between the output impedance Z L and the electric power system impedance Z S determines the edge frequencies of the low-pass irregular analog filter. It is given by To verify the validity of the redesigned low-pass irregular analog filter, a calculation was carried out with the HK software [38] when normalized values of Z S and Z L are considered (i.e., Z S = 2 Ω and Z L = 1 Ω). It resulted in F (f ) = ε(f 2 + 1) 2 = ε(f 4 + 2f + 1), P (f ) = 1, ε = 0.353553390593, and E(f ) = ε(f 4 + 2.4467f 3 + 4.9932f 2 + 5.0950f + 3). Applying the Ladder software [38], we obtained the normalized values of the components of the low-pass irregular analog filter for Z L > Z S as in Fig. 8(a). Applying a similar redesign procedure and Z S > Z L , we see that normalized values of components are equal to the previously designed low-pass irregular analog filter because both of them are a mirror of each other, see Fig. 8(b). The values of each normalized component evaluated by the Ladder software are listed in Table III for Z L > Z S (25 − 50 Ω) and in Table IV for Z S > Z L (100 − 50 Ω).
Finally, to obtain the real values of the normalized components, we need to apply the following equations: and where L ′ n and C ′ n is the normalized value of the inductor and capacitor, respectively, that are calculated by the HK and Ladder software, and f c ∈ {50 MHz, 100 MHz, 500 MHz} is the cut-off frequency. The index n denotes the n th inductor and capacitor of the low-pass irregular analog filter.
2) Low-pass Chebyshev analog filter: The choice of the low-pass Chebyshev analog filter for impedance matching with a 1 : 1 ratio Z S = Z L is based on the characteristics of access impedance of electric power systems detailed in [31]. Analyzing the Cumulative Density Function (CDF) of the access impedance reactance, we can see an inductive behavior of this reactance. Note that [31] showed an inductive behavior in 73% of the measured access impedance of electric power systems for the frequency band of 2−500 MHz. Consequently, the aim is to design a low-pass analog filter with a series inductor that can help us deal with the reactance characteristic of access impedance in electric power systems.
According to simulations carried out in the Advanced Design System (ADS) software to design this analog filter, we can see that the first inductor, the component L 3 in Fig. 3, in the low-pass Chebyshev analog filter has a higher inductance value compared to the other analog filter structures, such as Elliptical, Butterworth, Gaussian, and Inverse Chebyshev. As a consequence, it facilitates the design of an impedance matching circuit. Based on [39], we can make the value L 3 , which is a component of the low-pass Chebyshev analog filter, close to the reactance of the access impedance of electric power systems [31], and consequently, impedance matching improves. The analog filter consists of a Ladder network formed using series inductances and shunt capacitances (L 3 , L 4 , L 5 , C 4 , and C 5 ), see Fig. 3, for performing 50 − 50Ω impedance matching. The values of each component evaluated by the ADS software are listed in Table I.
3) Scattering parameter analysis: Figs. 9, 10 and 11 show the magnitudes of the scattering parameters (i.e., reflection parameters, S 11 (f ) and S 22 (f ), and transmission parameters, S 12 (f ) and S 21 (f )) of the three analog filters, which were designed to constitute the prototype of the adaptive PLC coupling circuit, which covers the three frequency bandwidths. These magnitudes were obtained by using the software ADS.
The magnitudes that cover the frequency band of 2 − 50 MHz, as shown in Figs. 9a and 9c, refer to the lowpass irregular analog filters with an input impedance of 25 Ω and 100 Ω, respectively, while Fig. 9b refers to the low-pass Chebyshev analog filter. Note that the magnitudes of S 12 (f ) and S 21 (f ) are around 0 dB. Also, the low-pass Chebyshev analog filter offers a better roll-off factor and a stop-band attenuation 11 dB higher than the low-pass irregular analog filters in 100 MHz. Concerning the magnitude of S 11 (f ) and S 22 (f ), we see that the low-pass irregular analog filters achieve a better impedance matching in the middle of the frequency band, see Figs. 9a and 9c. Also, the low-pass irregular analog filter with input impedance of 100 Ω, see Regarding the frequency band of 2 − 100 MHz, Figs. 10a and 10c show magnitudes of the scattering parameters of the low-pass irregular analog filters with an input impedance of 25 Ω and 100 Ω, respectively, while Fig. 10b shows the same magnitudes for the low-pass Chebyshev analog filter. All analog filters attain magnitude of S 12 (f ) and S 21 (f ) around 0 dB in the pass-band (i.e., 2 − 100 MHz). For the entire stop-band, the low-pass Chebyshev analog filter offers a better roll-off factor and attains attenuation of 9 dB in the stop-band better than the others. Similarly, the low-pass irregular analog filters (Figs. 10a and 10c) attain a better impedance matching in the middle of the frequency band. Also, the low-pass irregular analog filter with input impedance of 100 Ω, see Fig. 10c, shows magnitudes of S 11 (f ) and Focusing on the frequency band of 2 − 500 MHz, Figs. 11a and 11c the magnitudes of scattering parameters of the lowpass irregular analog filters with the input impedance of 25 Ω and 100 Ω, respectively, while Fig. 11b shows the same magnitudes for the low-pass Chebyshev analog filter. Regarding the pass-band, we see that all analog filters attain magnitudes of S 12 (f ) and S 21 (f ) around 0 dB. Paying attention to passband, we see that the low-pass Chebyshev analog filter offers a better roll-off factor and attains attenuation 9 dB better than the low-pass irregular analog filters in 500 MHz. Also, the low-pass irregular analog filters with the input impedance of 100 Ω offer the worse stop-band attenuation (−28 dB) in 500 MHz. Analyzing the magnitude of S 11 (f ) and S 22 (f ), we see that the low-pass irregular analog filters (Figs. 11a and 11c) attain the best impedance matching in the middle of the frequency band. The low-pass irregular analog filters with input impedance of 25 Ω, Fig. 11a, attains the best magnitudes of S 11 (f ) and S 22 (f ) in 301 MHz (−29 dB), and the low-pass Chebyshev analog filter showed the lowest magnitude of S 11 (f ) (−9 dB in 450 MHz) and S 22 (f ) (−56 dB in 302 MHz). The low-pass irregular analog filters with input impedance of 25 Ω, see Fig. 11c, shows the worse performance in terms of magnitude of S 11 (f ) and S 22 (f ), with −16 dB in 300 MHz. Again, we can state that impedance matching for 100 − 50 Ω is the best while the worst is obtained for 25 − 50 Ω.

D. Control unit
According to the Strategy #2, the analog filter yielding the best impedance matching between a PLC transceiver and electric power system is chosen by the control unit. Based on the voltage signal strength at the output of the impedance matching circuits bank, the control unit determines the Switch Bank position and chooses the impedance matching circuit.
The flowchart in Fig. 12 refers to the algorithm implemented in the control unit. The start point of the algorithm, when the adaptive PLC coupling circuit is connected to an electric power system, consists of switching the M = 3 impedance matching circuits, and the measured quantities are based on (7) because it informs the strength of the signal at the output of the Switch Bank #2. To reduce computational complexity, we used the average signal value (i.e., the average voltage value) in this implementation because it demands less computational complexity than the average power and consequently allows us to use a low-cost microcontroller.
For the sake of simplicity, from now on, the mean voltage level will be mentioned only as a voltage level. The voltage value for each impedance matching circuit is memorized, and the best circuit is selected as the one yielding the largest voltage level at the output impedance matching circuit bank. After that, the microcontroller selects the best circuit (analog low-pass filter). Following this first step, the microcontroller keeps checking the voltage level read by the analog-to-digital converter (ADC). If the voltage level drops significantly compared to with the best-stored levels, then a searching process for the best impedance matching circuit starts again, and it returns to the start point after a new choice is made. Furthermore, periodic searches are carried out, returning to the start point to ensure that the current impedance matching circuit is still the best.
1) Microcontroller: For controlling the switching of analog filters, a low-cost ESP-8266 microcontroller [40], which owns an integrated 10 bits ADC and general purpose input/output (GPIO) pins, is chosen. The microcontroller is attached to the connectors CN 1 and CN 2 and has three LEDs (LED 1 to LED 3 ) to visually indicate the analog filter being used. Three GPIO connections are used to command each switch, and, as a consequence, the selection of the desired analog filter is carried out based on the knowledge of the voltage level, which is acquired by the ADC device.
2) Logarithmic amplifier: Fig. 13 shows the schematic of the chosen logarithmic amplifier (AD 8307) [41] for sensing the strength of the voltage signal at the output of the Switch Bank #2 when N = 64. The capacitors C 8 and C 9 and the inductor L 8 comprises a narrowband analog filter designed to detect the frequency of the maximum gain of the low-pass irregular analog filter and low-pass Chebyshev analog filter calculated by (f c /1.6376) [42], [43], where f c is the cutoff frequency. The design of this band-pass analog filter was carried out using the ADS software. For instance, to design a 50 MHz band-pass analog filter for the adaptive PLC coupling circuit, the center frequency of the band-pass analog filter should be designed for 50 MHz/1.6376 = 30.53 MHz. Tab. V lists the values adopted for C 8 , C 9 and L 8 components for each frequency band.  Fig. 12: Flowchart of the algorithm implemented in the Control Unit. 2-50 MHz, 2 − 100 MHz, and 2 − 500 MHz. The equipment used to carry out the analysis is the vector network analyzer (VNA) N 9912A Agilent, which frequency band ranges from 2 MHz up to 4 GHz [44]. For this purpose, the scattering parameters S 11 (f ) and S 21 (f ) of the adaptive PLC coupling circuit are compared to those obtained with the nonadaptive PLC coupling circuit, which has its input and output impedance equal to 50 Ω and makes use of a 5 th order elliptic analog filter to perform impedance matching. The scattering parameters S 21 (f ) and S 11 (f ) are obtained in terms of the 50 Ω impedance of the VNA [45].
A setup arrangement for measuring scattering parameters is shown in Fig. 14. The curves of the scattering parameters, which are measured between the adaptive PLC coupling circuits, were performed in a 127 V rms 60 Hz electric power circuit with a power line of 15 meters in length and constituted by two parallel wires with 2.5 mm in diameter. The distance of 15 meters agrees with the distances observed in the average area of Brazilian apartments [46].
The measurement experiment was carried out using the following three setup arrangements: • Setup #1: the use of the experimental setup with two the non-adaptive PLC coupling circuits with input and output impedance equal to 50 Ω, which will be called from now on as the non-adaptive PLC coupling circuit of 50 Ω. These coupling devices are connected to both sides of electric power systems. • Setup #2: the use of the experimental setup with the non-adaptive PLC coupling circuit of 50 Ω, which is connected to one transceiver and an adaptive PLC coupling circuit (designed as a low-pass irregular analog filter and low-pass Chebyshev analog filter), which is connected to the other transceiver. The adaptive PLC coupling circuits own input impedance equal to 25 Ω, 50 Ω and 100 Ω and output impedance equal to 50 Ω. From now on, we will be called just as the adaptive PLC coupling circuit of 25 Ω, the adaptive PLC coupling circuit of 50 Ω or the adaptive PLC coupling circuit of 100 Ω, depending on which analog filter is selected. • Setup #3: the use of the experimental setup with two adaptive PLC coupling circuits connected to both sides of electric power systems with the same input impedance (25 Ω with 25 Ω, 50 Ω with 50 Ω, and 100 Ω with 100 Ω) connected. Notice that the non-adaptive PLC coupling circuit of 50 Ω may present different curves from the adaptive PLC coupling circuit of 50 Ω, due to their different construction. The former uses an elliptic analog filter, while the latter applies a low-pass Chebyshev analog filter.
Vector Network Analyzer S11 S11 S12 S12  Regarding the frequency of 2 − 500 MHz, Fig. 15(c) shows that the magnitude of S 12 (f ) varies between −15 dB at the frequency of 2 MHz and −53 dB at the frequency of 500 MHz. Also, it is clear that the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) offers the best insertion loss, varying between −15 dB at the frequency of 2 MHz and −45 dB at the frequency of 500 MHz. At the cut-off frequency of 500 MHz, the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) yields a sharp roll-off, which varies between −45 dB and −65 dB and provides the lowest attenuation. The adaptive PLC coupling circuits with input impedance equal to 25 and 50 Ω (lines with △ and ⋄ marks, respectively) show the worst gain in the whole frequency band.

B. Comparison between Setup #1 and Setup #3 in terms of
The analysis of this subsection shows the results obtained from the measurements of the S 21 (f ) parameter using Setup #3. The results achieved using Setup #1 are also presented for comparison purposes. Fig. 16(a), (b) and (c) depicts the measurement of the S 21 (f ) scattering parameter comparing both setups at the frequency band of 2−50 MHz, 2−100 MHz and 2 − 500 MHz, respectively. The line with • marks is the measurement acquired using Setup #1, while the lines with △, ⋄ and marks are the measurements obtained using the Setup #3 with the input impedance of the adaptive PLC coupling circuits equal to 25 Ω, 50 Ω and 100 Ω, respectively. Fig. 16(a) shows that, at the frequencies between 2 MHz and 15 MHz, the behavior of the magnitude of the scattering parameter of the non-adaptive PLC coupling circuit of 50 Ω and the adaptive PLC coupling circuits of 25 Ω, 50 Ω or 100 Ω are very similar. However, at the frequencies between 15 MHz and 40 MHz, the adaptive PLC coupling circuits of 50 Ω and 100 Ω (lines with ⋄ and marks, respectively) have a better insertion loss varying between −9 dB and −14 dB in comparison with the non-adaptive PLC coupling circuit of 50 Ω and the adaptive PLC coupling circuit of 25 Ω. As can be seen, at the frequencies between 42 MHz and 50 MHz, the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) has the insertion loss with better gain and shows a better roll-off at transition band and attenuation at the stopband frequency.
The results depicted by Fig. 16(b) shows that the adaptive PLC coupling circuits of 50 Ω and 100 Ω (lines with ⋄ and marks, respectively) have better insertion loss compared to with the adaptive PLC coupling circuit of 25 Ω and the nonadaptive PLC coupling circuit of 50 Ω (lines with △ and • marks, respectively) at the frequency band 2 MHz up to 100 MHz. Moreover, the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) presents a better roll-off at transition band and attenuation at the stop-band frequency.  show that the adaptive PLC coupling circuit of 25 Ω (line with △) presents the worst results in all aspects, analyzing the band-pass, transition band and stop-band frequencies.
Finally, Fig. 16(c) depicts that the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) has a better insertion loss and attenuation at the stop-band frequency compared to with the adaptive PLC coupling circuits of 25 Ω, 50 Ω and 100 Ω (lines with , △, ⋄ and marks, respectively). The adaptive PLC coupling circuit of 100 Ω (line with marks) has the second best results in terms of magnitude of the scattering parameter at the band-pass of 2 MHz up to 500 MHz and the adaptive PLC coupling circuits of 25 and 50 Ω (lines with △ and ⋄ marks, respectively) show the worst results.
The previous subsections have shown that the inductive behavior of electric power systems causes higher attenuation in the magnitude of the scattering parameter of the non-adaptive PLC coupling circuit of 50 Ω and the adaptive PLC coupling circuits of 25 Ω, 50 Ω, and 100 Ω. Similar behaviors were noted in the results obtained with Setup #1 and Setup #3.
C. Comparison between Setup #1 and Setup #2 in terms of S 11 (f ) This subsection presents the results obtained from the measurements of the return loss S 11 (f ) parameter using Setup #2. The results achieved using Setup #1 are also shown for comparison purposes. Figs. 17(a)-(c) show the magnitudes of S 11 (f ) related to both setups at the frequency bands of 2 − 50 MHz, 2 − 100 MHz, and 2 − 500 MHz, respectively. The line with • marks is the measurement acquired using Setup #1. On the other hand, the lines with △, ⋄ and marks are the measurements obtained using Setup #2 with the input impedance of the adaptive PLC coupling circuits equal to 25 Ω, 50 Ω and 100 Ω, respectively.   The curves in Fig. 17(a) aims to show the magnitudes of S 11 (f ). The ripples in the reflection coefficients range between −2.5 dB at the frequency of 15 MHz and −37 dB at the frequency of 50 MHz. We also observe that the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks) presents the best impedance matching at the frequency of 30.5 MHz, which is the frequency designed to obtain the best impedance matching (50 MHz/1.6376), as discussed in Section IV-C. As a result, it is found that the impedance matching is also noticed at different frequencies in the Fig. 17(a). At the frequency of 6 MHz, the adaptive PLC coupling circuit of 100 Ω (the line with marks) achieved a better impedance matching, equal to −23 dB, when compared to with the non-adaptive PLC coupling circuit of 50 Ω and the adaptive PLC coupling circuits of 25 Ω and 50 Ω. The same analysis can be noticed for the frequencies of 12 MHz and 24 MHz where the nonadaptive PLC coupling circuit of 50 Ω (the line with • marks) attained a good impedance matching. At the designed cutoff frequency, 50 MHz, the adaptive PLC coupling circuit of 100 Ω achieved a better impedance matching compared to the other PLC coupling circuits.
As well as in Figs. 17(a), Fig. 17(b) also presents a similar return loss S 11 (f ) scattering parameter for all couplers analyzed, exhibiting ripples in the reflection coefficients. The ripples vary between −2 dB at the frequency of 22 MHz and −42 dB at the frequency of 98 MHz. We also observe that the adaptive PLC coupling circuit of 100 Ω (line with marks) has the best impedance matching, showing the best return loss S 11 (f ) scattering parameter at the whole frequency band. At the frequency of 61 MHz, where the adaptive PLC coupling circuit of 25 Ω, 50 Ω and 100 Ω filters were designed to obtain the best impedance matching (100 MHz/1.6376), the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks) attained the best result, as well as, at the frequencies of 7 MHz, 12 MHz, 22 MHz and 56 MHz. At the frequency of 98 MHz, near the designed cut-off frequency 100 MHz, the non-adaptive PLC coupling circuit of 50 Ω (the line with •), attained the best impedance matching.
Interesting results can be observed analyzing the return loss in Fig. 17(c). The best impedance matching is obtained by the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks) while the adaptive PLC coupling circuit of 25 Ω (line with △ marks) and the non-adaptive PLC coupling circuit of 50 Ω (line with • marks) show the worst impedance matching. The adaptive PLC coupling circuit of 100 Ω (lines with marks) shows a good impedance matching, equal to −30 dB at the frequencies 198 MHz and at the cut-off frequency and −17 dB at 505 MHz. As can be seen in Fig. 17(c), the impedance matching is not achieved at the frequency (500 MHz/1.6376) where the analog filters were designed to obtain the best impedance matching.

D. Comparison between Setup #1 and Setup #3 in terms of S 11 (f )
This subsection presents the results obtained from the measurements of the return loss S 11 (f ) scattering parameter using Setup #3. The results achieved using Setup #1 are also presented for comparison purposes. Figs. 18(a), (b) and (c) depict the measurement of the return loss S 11 (f ) scattering parameter comparing both setups at the frequency bands of 2 − 50 MHz, 2 − 100 MHz and 2 − 500 MHz, respectively. The line with • marks is the measurement acquired using Setup #1, while the lines with △, ⋄ and marks are the measurements obtained using Setup #3 with the input impedance of the adaptive PLC coupling circuits equal to 25 Ω, 50 Ω and 100 Ω, respectively.   As can be seen in Fig. 18(a), the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks) and PLC coupling circuit of 25 Ω (line with △ marks) presented the worst impedance matching at the frequency between 23 MHz and 50 MHz. On the other hand, the adaptive PLC coupling circuit of 100 Ω (line with marks) shows the best impedance matching in the whole frequency band. The non-adaptive PLC coupling circuit of 50 Ω achieved the best impedance matching at the frequency of 38 MHz, equal to −45 dB and at the cut-off frequency 50 MHz, equal to −31 dB.
The results obtained in Fig. 18(b) shows that the adaptive PLC coupling circuit of 100 Ω (line with marks) attained the best impedance matching at the frequency band of 2 MHz until 82 MHz. However, the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks) has the best impedance matching in the frequency between 82 MHz until 100 MHz. As can be seen between 50 MHz and 70 MHz, the values of the return loss S 11 (f ) scattering parameter has the values near 0 dB which represents the total reflection of the S 11 (f ) scattering parameter due to impedance mismatching between two PLC coupling circuits. Based on Fig. 18(c), we can see that the best impedance matching is obtained by the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks). At the frequency of 199 MHz the value achieved, equal to −50 dB, is the best impedance matching in the whole band. The non-adaptive PLC coupling circuit of 50 Ω (line with • marks) shows the worst impedance matching and the results of the adaptive PLC coupling circuit of 100 Ω (line with marks) presents the impedance matching results near to the adaptive PLC coupling circuit of 50 Ω (line with ⋄ marks). According to Figs. 18(a), (b) and (c), the impedance matching designed for the low-pass irregular analog filter calculated for the frequencies (50 MHz/1.6376), (100 MHz/1.6376) and (500 MHz/1.6376) is not achieved in all PLC coupling circuits considered in the setups.

E. General Comments
The discussed results have shown that impedance matching circuits bank improve the power transfer between PLC transceivers and electric power systems when broadband PLC systems are considered; however, the dynamics of LV electric power systems make rather tricky to match the impedance accordingly at all times. Comparing the numerical results provided by the measurement setups, we note how difficult it is to match the impedance between two PLC coupling devices. Also, we have noticed that all magnitude curves are very similar to each other and for some frequencies, a good impedance matching can be attained. Overall, impedance matching using an adaptive PLC coupling circuit is challenging; however, it can offer improvement in comparison to the non-adaptive PLC coupling circuit. Furthermore, we have shown that the attenuation between PLC couplers can reach 60 dB in very specific and narrow frequency band in the pass-band. Also, the highest attenuation is observed at the upper frequencies of the pass-band, which agrees with the low-pass characteristic of electric power systems.

VI. CONCLUSION
This work has introduced theoretical justifications for using the analog filter bank approach to perform impedance matching between PLC transceivers and electric power systems. Based on the principle of divide and conquer together with the coherence time and the coherence bandwidth, we came up with two strategies for prototyping impedance matching circuits based on the analog filter bank approach when the time × frequency dynamics of access impedance in electric power systems are considered.
Based on experimental results, we have shown that the proposed analog filter bank approach offers better performance than usual. Also, we showed that the impedance matching between a PLC transceiver and an electric power system using the proposed analog filter bank approach is not a simple task to be accomplished. Moreover, impedance matching between two or more adaptive PLC coupling circuits may be a difficult task to be accomplished due to the coordination among them. It must be carefully addressed.
Overall, we have noticed that impedance matching based on the analog filter bank approach is an interesting research direction because there is room for remarkable improvements concerning the designs of analog filters and control unit.