DESIGN AND PROTOTYPING OF AN SDH-E1 MAPPER SOFT-CORE

- This paper describes the design and prototyping of EMS, a telecommunication intellectual property soft-core developed in the scope of industry-academia cooperation. EMS performs insertion (mapping) and extraction (demapping) of EI channels into/from Synchronous Digital Hierarchy (SDH) frames. The basic SDH frame is transmitted in 155.52 Mbps rate, allowing to pack up to sixty-three 2.048 Mbps El channels. El channels belong to the Plesiochronous Digital Hierarchy (PDH). The paper addresses the solution of several synchronization problems implied by the El channels mapping/demapping process. EMS was fully described in RTL VHDL. It was functionally validated by simulation and prototyped in FPGA platforms. Together with the exploration of the techniques involved in embedding PDH into SDH frames, another contribution of the work is the availability of a reusable and parameterizable telecom core with high performance, low latency, and small size.


INTRODUCTION
Over the last three decades, communication networks are evolving from analog to digital [I], which results in better transmission quality and larger bandwidth.In many areas, this technological change significantly boosted telecommunication systems research.With the advent of the WorId Wide Web comes an unprecedented increase in data traffic.The telecommunication systems complexity is growing faster, due to: (i) media and protocol diversity; (ii) applications nature variety; (iii) increased data communication speed.To cope with these fast changing scenarios, new telecommunication technologies are necessary.The Synchronous Digital Hierarchy is one example technology, due to its high data communication speed and high capacity to pack telecom protocols with different natures, like El, ATM and others.
This work introduces EMS, an EI channel MapperlDemapper into/from SDH frame.EMS is an intellectual property (lP) soft-core developed in the scope of industry-academia research and development cooperation.EMS is a successor of an EI IP soft-core design [2] developed within the scope of the same cooperation.An lP core is a pre-designed and pre-verified hardware module used in combination to compose larger circuits, typically custom VLSI integrated circuits or large programmable devices, such as multimillion-gate FPGAs.According to availability, IP cores can be classified into soft, firm or hard cores [3].Soft-cores are open-source codes, enabling high flexibility.Soft core design may not guarantee some functionality, such as exact timing in the final implementation.IP cores are increasingly important resources for complex digital systems design in general and particularly for telecom systems.According to ITRS report [4], by 2012, 90% of complex silicon chips surface will be composed by cores.In addition, approximately 50% of the programmable devices sold today are used in telecom applications [5].
The goal of this paper is to present the design of the EMS core.The main contributions are: (i) the design of an IP soft-core compliant with specific ITU-T standards [6][7] [8]; (ii) the prototyping of the system in hardware to guarantee timing constraints using Xilinx Virtex FPGAs; (iii) present results of accurate buffering analysis to perform EI mapping and demapping into/from SDH frames; (iv) make available a design with small footprint, which enables straightforward scaling and IP reuse in larger circuits.
The rest of this paper is organized as follows.Section 2 summarizes some important aspects of the plesiochronous digital hierarchy, which defines the characteristic of El carriers.In Section 3, some basic concepts of SDH are explained.Section 4 presents reviews previous works related to SDH mappers.Section 5 introduces the EMS architecture.Section 6 describes the EMS validation and prototyping, while Section 7 presents some conclusions and future work.

PLESIOCHRONOUS HIERARCHY
The term plesiochronous describes communication system where transmitted signals have the same nominal digital rate but are synchronized with different clocks.The Plesiochronous Digital Hierarchy (PDH) is a hierarchy of data and voice transmission systems that communicate using plesiochronous synchronization.PDH is a conventional multiplexing technology for network transmission systems.
European/South-American and North-American/Japanese versions of the PDH system differ slightly, but the operating principles are the same.North-American/Japanese basic data transfer rate is a stream transmitted at 1.544 Mbps, called a T1 channel.The European/South-American basic data transfer rate is a data and voice stream of 2.048 Mbps, namely El channel.For voice transmission, an El channel is broken down into 30 data and voice channels of 64 Kbps plus 2 64 Kbps channels used for synchronization and signaling.Each channel in a frame contains 8 bits and is called a time slot.Therefore, a frame contains 256 bits.Each time slot corresponds to a 64 Kbps channel carrying 8 bits of either data or an 8 KHz digitalized voice sample.Time slots are combined using Timing Division Multiplexing (TDM) at 2.048 MHz.Consequently, a frame is transmitted each 125 IJ.s.Multiple frames are grouped to transport alignment, error detection and service information.Eight consecutive frames constitute an El submultiframe (SMF) structure.Two consecutive El SMFs form an El multiframe (MF).EI carrier equipment transmits and/or receives an MF each 2 ms.The El rate is allowed to vary ± 50 ppm, which is equivalent to ± 102.4 bps.This means that different EI data streams can be running at slightly different rates.
PDH can combine multiple El channels generating other data and voice streams, such as 8 Mbps (E2), 34 Mbps (E3), 140 Mbps (E4) and 565 Mbps (E5) which are used in several kinds of communication systems.As an instance, 565 Mbps is typically used to transmit data over an optic fiber system for long distance communication.

SYNCHRONOUS HIERARCHY
The Synchronous Digital Hierarchy (SDH) and the Synchronous Optical NETwork (SONET) are hierarchies used in Europe/South-America and North-America/Japan, respectively.Both systems employ synchronous time division multiplexing techniques to transmit different tributaries (EI, Ethernet, ATM, etc) through the same physical channel.A primary goal in the development of the SDH/SONET formats is to define a synchronous optical hierarchy with sufficient flexibility to carry payloads of different types.SONET and SDH are based on transmission at rates that are integer multiples of 51.840 Mbps.SONET basic frame structure is called synchronous transport signal level one (STS-l).SDH basic modular signal is called synchronous transport module level one (STM-I).The STM-I rate is an extension of the basic STS-I (for this reason also called STM-O) and operates at 155.52 Mbps, carrying three interleaved STS-l frames.
Synchronous hierarchies differ from PDH in the exactness of data transport rate.SDH systems are tightly synchronized to network base clocks, making the entire network operate synchronously.The structure of SDH synchronization network (SSN) is founded on master-slave mode hierarchy of clock.The SSN highest hierarchy level is performed with a high precision clock defined as primary reference clock (PRC) [9] and is generally implemented by atomic frequency oscillators.The remaining of the hierarchy is organized as a tree.The reference timing-signal generated by PRC is distributed to the clocks of lower hierarchy levels, which are named slave clocks (SCs).SC tracks the reference-timing signal by means of phase-locked loop (PLL) systems.
This work focuses only in the path highlighted in Figure l.The El channel is packed into C-12, implying the insertion of a control and stuffing byte.C-12 is mapped into YC-12.A pointer implements virtual container alignment, generating TU-l2.Three TU-12 are multiplexed into TUG 2, seven TUG-2 are multiplexed into TUG-3, and three TUG-3 are multiplexed into YC-4.Pointers implement virtual container alignment, generating the AU-4.The AU-4 is grouped into the AUG, and the AUG is multiplexed into one or more STM-ls.Each frame transports 19,440 bits (270 x 9 bytes) at a 155.52 Mbps rate, implying a frame period of 125 Ils.Four frames compose a super-frame (SF), the highest structural level of SOH STM-l.As depicted in Figure 3, the STM-l payload pointed by the JO byte may float inside the STM-l frame.J 1 marks the start point of each VCA payload inside the STM-l payload.In each SF, there are four different kinds of TU-12 PTR (VI, V2, V3, and V4).VI and V2 pointers are joined to compose the V5 address, which marks the beginning of C 12. When POH and SOH clock frequencies are synchronized, there are 1024 bits of useful data transmitted in 4 El channels.Otherwise, it is possible to add or subtract R -stuffing b)1e r -stuffing hit one bit from each SF.The C-12 structure of S~' merges two or three extra bytes with 32 or 31 El bytes.The first C-12 encloses two stuffing bytes and an El channel.The second and the third C-12 of each SF contain one control byte, one stuffing byte and one El channel.The last C-12 of each SF encloses one control byte, seven data bits and a justification opportunity bit, one stuffing byte and 31 bytes of E I channel.The majority of CIS and C 2 s bits implies positive or negative frequency justifying.This means that when two or more Cj bits are 1, the Sj bits are valid data.This, in tum, means that 1025 bits of data are available for SF.On the other hand, if two or more Cj bits are 0, the Sj bits are stuffing bits, meaning that 1023 bits of data are available for SF.The number of bytes implies slight changes of clock frequency.For instance, 1025 bits implies 2,050 KHz and 1023 bits implies 2,046 KHz.This frequency change allows mapping/demapping a POH frame into/from an SOH frame without data loss.

RELATED WORK
The demand for telecommunication services leads to a significant offer of SOH systems in the market [10][11] [12].Each distinct equipment presents its own distinguishing features, different prices, and use cases.In addition, the high complexity of SOH systems like asynchronous to synchronous mapping, design for testability, abstract modeling and others, drives the research in this field.Lin et al. (1994) propose a flexible architecture for implementing an SOH STM-l Add-Orop multiplexer [13].They implemented an internal Telecom Bus-like architecture, to provide El and E3 communication services between internal and external circuits (adapters/converters).Yongming et al. (1996) considered three ways of mapping asynchronous 2.048 Mbits/s tributaries into SOH VC-12: asynchronous, bit synchronous and byte synchronous [14].The authors focus on the asynchronous mapping, discussing positive/zero/negative justification to improve the capacity of elastic buffer store.Fuqiang et al. (1996) provide a similar analysis, quantifying the best elastic buffer sizes for POH to SOH and SOH to POH conversions [15].Xiaoru and Lieguang (1996) prototyped and verified an SOH STM-l in 8 3190/3090 Xilinx FPGAs [16].The final target implementation was a O.5llm three-layer CMOS gate array.Thalmann et al. (1999) report an architecture of an Add-OroplTerminal-Multiplexer for SOH, allowing to integrate all digital functions into one ASIC [17].The idea is based in two approaches: buffer usage optimization and embedded processor, which substitutes various large hardware blocks.
Clauberg et al. (1999) introduced a scalable modular architecture for SOH/SONET technology, by exploiting the regular multiplexing principle inherent to this hierarchy [18].They demonstrated the feasibility of their architecture with a framer chip, able to handle 4 STM-l and variations of STM-4.
Herkersdorf et al. (2000) complemented Clauberg works by covering the mapping of ATM, IP and T IIT3 traffic streams into SOH/SONET ranging from OC-l to OC-48/STM-16 [19].Rower et al. (2000) implemented an SOH/SONET input block using a new paradigm called programmable intellectual property [20].In it, modules can be reconfigured by downloading new software versions into IP embedded processors.
Peng, Oepeng and Lieguang (2000) developed THXC, an SOH cross-connected ASIC with an embedded BIST circuit [21].THXC is programmable and monitored by an external computer, designed to allow various switching rates and enables cascade connections among several identical chips.
Silveira and Van Noije (2000) presented the modeling of an El mapper for SOH Systems, pointing out the difficulties to implement them, due to the synchronization mechanisms and the nature of the POH infornlation carried in SOH frames [22].
Baechtold et al. ( 2001) implemented a single-chip for 4xOC-3c, OC-12c SOH/SONET framing [23].The chip features: low power consumption, integrated clock recovery that fulfils the ITU-T, Bellcore and ANSI jitter requirements, and functions to enable low-cost digital cross connect and add/drop multiplexing systems.
The multiplexing section overhead (MSOH) is a central part of SOH circuits since it treats many frame errors.Torres et al. (2003) presented an MSOH processor for STM-O/STS-l to STM-4/STS-12 [24].Their work purpose was to show the requirements specification, architecture and verification of such systems.
The present work introduces the EMS architecture, which is similar to Peng et al. ( 2000) system with the scalability introduced by Clauberg et al. (1999).In addition, the proposed approach is distinct from that of Yongming et al. (1996) and Fuqiang et al. (1996), achieving better elastic buffers sizing for PDH to SOH mapping and vice-versa.

THE EMS ARCHITECTURE
EMS is a scalable architecture, allowing from 1 to 63 El channels mapping/demapping into/from an SDH frame.The smallest functional EMS operates with one El channel and is called Basic EMS, or simply BEMS.When EMS operates with full capacity (63 El channels), it is capable of dealing with an entire SOH STM-l being called in this case STM-l EMS, or simply SEMS.
The BEMS external interface is comprised by three signals sets as depicted in Figure 4 and described    To Implement EI channel mappmg mto SDH frames, the EMS core adds data from an El channel (ElIN signal) to the Telecom Bus (DTBDATAOUT signal).The El demapping from SOH is implemented by receiving data from the Telecom Bus (DTBDATA signal) and mapping these to an El channel (EIOUT signal).The selected EI channel is addressed by the CHANNEL signal, which allows specifying one out of 63 channels.Five main modules and an auxiliary logic circuit (channel multiplexing, buffering, some control, and glue logic) compose the BEMS system (see Figure 5

COLUMNADDRESS MODULE
The ColumnAddress module receives as inputs the Telecom Bus control signals and generates the 11 pointer (payload start), VI pointer (TU-12 start) and the number of each column present in the payload (through the colurnnAddress signal).The column number allows the system to locate specific data of a channel in the Telecom Bus.The J I pointer corresponds to the first column number.The VI pointer allows the system to locate the VC-12 internal pointers (e.g.V5 pointer).

DELAY MODULE
The Delay module generates the replace control signal, responsible for defining the exact moment to insert data in a valid VC-4 column.

V5ENABLE MODULE
The V5Enabie module searches for valid data (dataValid signal) in the Telecom Bus.It also indicates the super-frame start (superFrarneStart signal).In addition, the V5Enabie module stores data from Telecom Bus and forwards them to VC12Drop and VC12Add modules.The module also detects valid columns through a 30 table mapped into a ROM-like structure.The table contains the first TU-12 channel number inside VC-4.For example, 9 ("000100 I") is the channel I address (second position of the partial VHDL code in Figure 7).The first word of the ROM corresponds to the channel a and is not used.The remaining 63 words correspond to each one of the 63 channels inside of VC-4 payload.
To extract VC-I2 from TU-I2 it is necessary to remove the bytes corresponding to V I, V2, V3 and V4 pointers that are represented by TU-12 PTR in Figure 2.These 4-byte positions are also provided by the colunmAddress signal.It is possible to observe in the partial VHDL code of Figure 9 that data is valid (da taValid =1) only if its address is different from the pointer addresses (I, 36, 72 and 108, respectively).In this case, a valid data is provided through the da taOu t signal.The V5 poinll'r address <represented by TU-12 POH in Figure 2) i~ computed joining the two least significant bits of the V I pOlntl'r and all eight bits of the V2 pointer.This results in an oll~l'l.shown in Figure 3.The VC-I2 address is obtained ~1;lrtin~ at the V2 pointer.For example, if the address or "S p,lInter is O. it means that this pointer is located in thl' rlr~t hyte after the V2 pointer.The pointers VI, V2. \', ;lIld "'+ must be skipped.When the offset is between () ;Ind''+.it means that V5 starts after V2 and before V.' l)lllllllT~.heing necessary to add 37 to the offset, to compose thl' ,•S pointer address.When the offset is between 35 and h().11 is necessary to add 38 to the offset, skipping thl' h~ ll'~ ahove the V3 pointer.The last case is when the olhl't i~ hetween 105 and 139.In this case, the offset must hl' (kcreased by 104.The resulting address will be between \ I and \'2 pointers.To search the 144 bytes of TU-12.thi~ nhllluk uses a counter called counter144 (see Figurl' 9l.Thl' counter144 counter is set to 0 when the V I poillll'l i~ detected.When the value of this pointer is equal to thl' ,•S pointer address, the beginning of the super frame is signakd through the superFrameS tart signal.

VC12DROP MODULE
The VC / ~ /)/11/1 lIlodule is responsible for extracting data from the Tl'ieclllll Bus and sending these to the El output channel.This module has an internal 64-bit circular FIFO buffer.The \\ rile pointer starts pointing at position O.To avoid data loss.the FIFO is read only when half of it is written.In other words, when the write pointer reaches position 32. the system starts the drop operation.After this, the FIFO reading operation is continuously active, and the reading clock is adjusted according to the difference between the write and read pointers, expressed by the DELTA signal.
This operation performs zero/negative/positive frequency justification.If DELTA is greater than the FIFO length, there is data loss.If DELTA is too smaiL the system can drop wrong data.The FIFO is dimensioned to avoid these problems.
A hysteresis mechanism was implemented to control the variation of the DELTA signal.It allows keeping minimal and maximal distances between read and write pointers before executing positive or negative justifications.Figure 10 shows this behavior.When the DELTA signal is between the minimal and maximal values, the system operates at the nominal frequency (2.048 MHz).To obtain a 2.048 MHz clock, the 65.536 MHz reference clock is divided by 32.When the DELTA signal reaches the maximal hysteresis value (48), the reading frequency (CKEIOUT signal) must be increased, and when the DELTA signal reaches the minimal hysteresis value (16), the reading frequency must be decreased, As depicted in Figure 3, the control justification bits (CIS and C 2 s) indicate if Sj and/or S~ are valid data bits, When the justification bits indicate valid data.bits contained in SI and/or S2 must be written to the FIFO.At the nominal frequency, only one of them is valid data.When SI and S2 are valid data, the amount of data to write in the FIFO is increased, and the DELTA signal is also increased, reaching the maximal hysteresis value.In this case, the reference clock is divided by 31, to obtain a 2.114 MHz frequency.This higher frequency reduces the DELTA signal to the normal range thus recovering the nominal frequency.When SI and S2 are not valid data bits, they are not written to the FIFO, making the DELTA signal reach the minimal hysteresis value.In this case, the CKEIOUT frequency must be decreased, dividing the reference clock by 33, to obtain a 1.986 MHz frequency, This lower frequency increases the DELTA signal to the normal range and as a result, the nominal frequency is recovered.

Reading frequency
The FIFO and hysteresis limits have to be dimensioned to avoid data loss, increased latency and memory usage.Short FIFOs can cause data loss, since bytes are written in burst using the 19.44 MHz clock frequency, while reading is continuously performed at a 2.048 MHz clock frequency.
Large FIFOs can increase memory cost and latency, and lead to improper operation.This is due to the time that the output frequency stays different from the nominal.Even with good FIFO dimensioning, the circuit may operate improperly due to the difference between minimum and maximum hysteresis limits.If the limits are too near or too far to/from each other, the output frequency will change too fast or too slow, violating the standard.This may, in tum, damage the signal recovery by an external El processing module.
Figure II shows the DELTA signal behavior for nominal clock operation, considering a FIFO with 64 bits, and maximum, medium and minimum hysteresis limits of 48, 32 and 16, respectively.Experimental data showed that the chosen hysteresis limits are adequate to respect ITU-T standards,  Figure 12 shows a partial simulation of the FIFO 1. DELTA is the difference between writeCont and operation.The readCount signal (read pointer) is readCount with regard to the FIFO size.Since the incremented at each CKEIOUT cycle, because the FIFO is buffer is implemented as a circular FiFO with 64 bits, always being read.The FIFO is written in bursts only when there are two formulae to compute DELTA: (i) If there is information to be dropped to the external EI readCount> writeCont, then DELTA f-FiFO size channel (i.e. when the flagwrite signal is equal to I).
readCount + writeCont (e.g.64 -42 + 12 = 34); (ii) Salient features in the simulation are numbered in Figure 12 Else DELTA f-writeCont -readCount (e.g.  13 shows another example simulation of the YC12Drop module, highlighting the frequency justification operation.The mark 1 shows the reference clock divided by 32 (limitCounterClock is 31, meaning that the range of the counter is from 0 to 31).Mark 2 shows the reference clock being divided by 33 (limi tCounterClock is 32).This new value of limi tCounterClock implies an increase of the clock period, meaning that fewer bits will be consumed by the E 1 output channel.

VC12ADD MODULE
The function of the VC12Add module is to insert data from an external El channel into the Telecom Bus.Data are received at CKElIN rate, an operating frequency that may vary.According to this variation, the VC12Add module executes the frequency justification through S\ and Sl justification opportunity bits, and C\ and C 1 justification control bits.The justification frequency is based on a hysteresis mechanism, analogous to the one used by the VC12Drop module.For data insertion, a 128-bit FIFO is needed, with minimum and maximum sizes of 32 and 96, respectively.The FIFO size of the VC12Add module is bigger than the corresponding FIFO of the VC12Drop module.This occurs as a result of the analysis of worst case synchronization conditions between PDH to SDH.These results pointed that during the Add operation the number of bits inserted may vary more widely than during the Drop operation.
When PDH and SDH clocks operate at their respective nominal frequencies, only one of SI or Sl is used as valid data bit.When the CKElIN frequency is higher than the nominal value, the amount of data written into the FIFO is increased and the DELTA signal reaches the maximum f hysteresis value.This increases the reading of El data input and adds to the amount of data into Telecom Bus, avoiding data loss.These extra Telecom Bus data must be inserted into S\ and Sl bits and the justification control bits must be set to 1.When the CKElIN frequency is below the nominal value, the amount of data written to the FIFO is less than the amount of data read.As a result, the DELTA signal reaches the minimum hysteresis value.To avoid reading incorrect data, it is necessary to decrease the Telecom Bus reading speed.Thus, S, and Sl bits are not filled with valid data and the justification control bits are set to O.
Figure 14 illustrates the DELTA signal behavior for the VC12Add module, considering nominal (2.048 MHz), high (2.050MHz) and low (2.046 MHz) EI input clock values.With CKElIN low frequency, there are more Telecom Bus data processing than EI input data generation.To avoid reading incorrect data, the VC12Add module reduces the number of valid data bits in each super-frame to 1023.Exactly the opposite happens when the EI input clock (CKElIN) has a frequency higher than the nominal value.To avoid data loss, the VC12Add module increases the number of valid data bits in each super-frame to 1025.

VALIDATION AND PROTOTYPING
One major difficulty with the EMS functional validation step is the number of simulation cycles needed to verify each design aspect, and the huge amount of output data produced and consumed during a simulation expected to provide even a moderate covering of the design characteristics.To alleviate the problem, external software was written.A parameterizable test pattem generator software creates test multiframes according to the parameters and the circuit under test.A test pattern analy::..er software compares simulation results (output files) against the input files and input parameters.
The validation process was conducted in three scenarios of increasing complexity.The first scenario is a loop verification, which considers the Telecom Bus and AddDrop circuits separately.The Telecom Bus circuit corresponds to the left side of Figure 5, comprising the buffer, column address and multiplexer.The second scenario, BEMS verification, evaluates the mapping/demapping of one EI channel into/from an SDH frame.The last scenario, global verification, evaluates the effects of mapping/demapping multiple E I channels into/from an SDH frame.
In the loop verification, depicted in Figure IS, the goal is to test the VCI2 FIFO operations and the SDH bypass path.The testbench code in this scenario has also a set of VHDL assert conditions to detect exceptions and critical operations (e.g.DELTA errors).

Figure l .
Figure l.SOH Multiplexing structure [6].The marked path underlines the focus of this work.

Figure 2 Figure 2 .
Figure 2 exemplifies one possible composition of the STM-l frame structure.This composition reflects how EMS operates.Each STM-l frame has 9 rows and 270 columns.Each column has a width of 1 byte.The first nine columns are transport overhead, combining a pointer (AU-4 PTR) and section overhead (SOH).SOH contains framing error monitoring and management.AU-4 PTR identifies the YC

Figure II .
Figure II.DELTA signal behavior for VC12Drop nominal clock, for different time scales.

Figure 15 -
Figure 15 -Loop verification for the functional validation process.

Table 1 .
in The first set, composed by RST_N, CK32_768 and CK65_536 signals, is used to perform system control and synchronization.The second set is composed by DTBYCK, DTBPAY, DTBJOJl, DTBDATA and DTBDATAOUT signals.These signals implement a partial Telecom Bus interface.Telecom Bus is a byte-wide parallel format that serializes and deserializes data and identifies the 10 and J 1 , pointers in the SDH frame, reducing the core operating frequency from 155.52 MHz to 19.44 MHz [11].The third set is composed by ElIN, CKEIIN, EIOUT, CKEIOUT and CHANNEL signals.These signals implement the El interface.

Table l .
Signals description of BEMS interface.
VC12Add and VC12Drop modules are encapsulated in a module called AddDrop.This hierarchical structure provides scalability to EMS.To increase the number of EI channels to n it suffices to instantiate the AddDrop module n times together with adding an extra structure to control DTBDATAOUT multiplexing.Figure6depicts SEMS, composed by 63 AddDrop modules.
): l.ColumnAddressidentifies the TU-12 start pointer in the Telecom Bus; 2. Delaysignals the moment to insert data in a valid VCA column; 3. V5Enabiehas three basic functions: (a) storing the SOH data when its address corresponds to the channel to be changed; (b) indicating when a column is valid; replac("lt"o

da Sociedade Brasileira de Telecomunicaeroes Volume 20 Numero 02, Agosto de 2005 2
. sliperFrameStart indicates the beginning of a super frame, pointing to the V5 pointer, that is equal to FF (FF is a value used just for simulation purposes): 3. data Valid indicates the occurrence of valid data in the Telecom Bus.Since this is a control byte (VC-12 POH), the flagwrite is not active and this infOlmation is not written to the FIFO: 4. data Valid indicates the occurrence of valid data in Telecom Bus.In this moment, Telecom Bus contains payload data, activating flagwrite; 5.There are valid data in Telecom Bus and this hexadecimal value (2A) is El payload infonnation, written in burst to the FIFO; 6.The data (2A) is extracted from the FIFO, and serially written into the El output channel.It is important to stress that this data is not the same data obtained in step 5. since there are other bytes in the FIFO with the same value.Figure 20 -0 = and explained below.20); Revista